1. Field of the Invention
The present invention relates to an apparatus for controlling the pulse width of an internal control signal used in a memory device using OCD (Off Chip Driver) calibration information, and a method thereof.
2. Description of the Prior Art
Recent high-integration and high-speed memory devices may differ greatly in performance according to their process variation. Particularly, output drives of the memory device that transmit data to an external system may differ greatly in driving force according to their process variation. Accordingly, from a DDR2 sync memory device, the driving capability of the output drive of the memory device is calibrated using OCD calibration information.
As is well known, the OCD calibration means that the external system checks the driving force of the output driver of the memory device caused by the process variation and calibrates the driving force of the output driver. Also, the OCD calibration information means the process skew information of the memory device that the external system obtains from the OCD calibration. Here, the process skew means the characteristic deviation of the respective element of circuit due to the process variation.
However, the conventional OCD calibration information has been used only to calibrate the driving force of the output driver of the memory device, and this causes internal circuits of the memory device to include the process skew according to the process variation. Hereinafter, the problems involved in the conventional memory device will be explained with reference to the accompanying drawings.
FIG. 1a is a view illustrating a unit cell, a sense amplifier, a word line WL, bit lines BL and /BL, and local input/output (I/O) lines LIO and /LIO of a conventional memory device. In FIG. 1a, if a column control signal YI is enabled, data on the bit lines BL and /BL are transferred to the local I/O lines LIO and /LIO. For reference, the data transferred to the local I/O lines are transferred to an outside through global I/O lines and an output driver.
FIG. 1b is a waveform diagram explaining the operation of the circuit of FIG. 1a. As illustrated in FIG. 1b, while the column control signal YI is enabled as a high level, the bit-line data amplified by the sense amplifier would be transferred to the local I/O lines.
However, if there is any process variation, the column control signal YI output from a circuit that generates the column control signal may present diverse process skews as shown in FIG. 2.
In FIG. 2, “20” denotes a fast skew of the column control signal YI, “21” denotes a typical skew of the column control signal YI, and “22” denotes a slow skew of the column control signal YI. Here, the fast process skew means that a signal processing speed of an internal control signal generation circuit that generates the column control signal YI is high, and the slow process skew means that the signal processing speed of the internal control signal generation circuit for generating the column control signal YI is low.
Generally, if the pulse width of the column control signal YI is narrow, the bit-line data cannot completely be transferred to the local input/out lines. By contrast, if the pulse width of the column control signal YI is wide, the generation time of the following control signal may be delayed and this may cause the data processing speed to be generally lower. Accordingly, it is preferable that the pulse width of the column control signal YI is kept constant. This may be applied to other internal circuits of the memory device in the same manner.
As described above with reference to FIGS. 1a, 1b and 2, the internal circuits of the memory device include the process skew according to their process variation, and thus a stable operation thereof cannot be secured.